In the field of manufacturing liquid crystal displays, after an array substrate is manufactured, an array test (AT) needs to be performed to detect whether a data line or a gate line in the array substrate is open, and the open data line or open gate line is repaired after a Data Open (DO) or Gate Open (GO) is detected. Therefore, during array test, the detection rate of DO and GO as well as the accuracy in detecting a defect position are vital to the post maintenance.
In an existing design of array substrate, as shown in FIG. 1, in general, one short circuit ring 20 is provided at an end (i.e., the end opposite to a source driving circuit) of each data line 10, all short circuit rings 20 are connected to the same common wire 30, and the short circuit ring 20 can conduct the instantaneous high voltage of static electricity existing in a display area out to the common wire 30, so as to dissipate the static electricity existing in the display area. However, since a plurality of short circuit rings 20 respectively provided at the ends of a plurality of data lines 10 are connected to the same common wire 30, when testing the plurality of data lines 10, a signal intrusion phenomenon may occur, thereby affecting the detection rate and accuracy of the array test.
The reason why a signal intrusion phenomenon occurs is as follows: since carriers can still pass through the channel of the thin film transistor in the short circuit ring 20 at a voltage of 0V, when testing the data lines 10, a high-level signal applied to the first data line 10 is conducted to the common wire 30 through the short circuit ring 20 provided at the end of the first data line 10, then flows onto a open data line 10 through the common wire 30 and the short circuit ring 20 provided at the end of the open data line 10, thus the signal intrusion phenomenon occurs to the open data line 10. This causes the open data line 10 that should not have a high-level signal to have a high-level signal, resulting in a failure to detect the disconnection of the data line 10, thereby affecting the detection rate and accuracy of the array test.